完善AMESim组件界面与仿真求解稳定性

tests/test_amesim_signal_components.py

@@ -20,6 +20,8 @@ class AmesimSignalComponentTests(unittest.TestCase):
         self.assertEqual(step.output_at(0.49), 0.2)
         self.assertEqual(step.output_at(0.5), 0.8)
         self.assertEqual(step.signal_output_values(0.5), {"out": 0.8})
+        self.assertEqual(step.signal_event_times(0.0, 1.0), (0.5,))
+        self.assertEqual(step.signal_event_times(0.5, 1.0), ())
 
 
     def test_ud00_output_interpolates_piecewise_signal(self) -> None:
@@ -38,6 +40,7 @@ class AmesimSignalComponentTests(unittest.TestCase):
         self.assertAlmostEqual(signal.output_at(2.5), 15.0)
         self.assertAlmostEqual(signal.output_at(5.0), 35.0)
         self.assertEqual(signal.signal_output_values(2.5), {"out": 15.0})
+        self.assertEqual(signal.signal_event_times(0.0, 5.0), (0.5, 1.5, 3.5))
 
     def test_ud00_can_cycle_active_stages(self) -> None:
         signal = AmesimUd00(
@@ -53,6 +56,7 @@ class AmesimSignalComponentTests(unittest.TestCase):
         self.assertAlmostEqual(signal.output_at(0.25), 2.5)
         self.assertAlmostEqual(signal.output_at(1.25), 12.5)
         self.assertAlmostEqual(signal.output_at(2.25), 2.5)
+        self.assertEqual(signal.signal_event_times(0.0, 5.0), (1.0, 2.0, 3.0, 4.0))
 
     def test_ud00_registry_rejects_fractional_stage_controls(self) -> None:
         with self.assertRaisesRegex(ValueError, "nstages must be an integer"):
@@ -91,6 +95,24 @@ class AmesimSignalComponentTests(unittest.TestCase):
         self.assertAlmostEqual(step.out.signal, 0.75)
         self.assertAlmostEqual(valve.res.signal, 0.75)
         self.assertAlmostEqual(valve.opening, 0.75)
+        self.assertEqual(resolver.event_times(0.0, 0.2), (0.1,))
+
+    def test_signal_resolver_event_times_are_sorted_and_deduplicated(self) -> None:
+        network = SimulationNetwork("signal-events")
+        network.add_component(
+            AmesimStep0("step_2", self.medium, initial=0.0, final=1.0, time=0.2)
+        )
+        network.add_component(
+            AmesimStep0("step_1", self.medium, initial=1.0, final=0.0, time=0.1)
+        )
+        network.add_component(
+            AmesimStep0("step_3", self.medium, initial=0.0, final=1.0, time=0.2)
+        )
+
+        resolver = SignalResolver(network)
+
+        self.assertEqual(resolver.event_times(0.0, 0.3), (0.1, 0.2))
+        self.assertEqual(resolver.event_times(0.2, 0.3), ())
 
 
 if __name__ == "__main__":