98 lines
3.7 KiB
Python
98 lines
3.7 KiB
Python
from __future__ import annotations
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import unittest
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from app.simulation.components.amesim.flow.orifices import AmesimPnvo001SignalOpening
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from app.simulation.components.amesim.signals.sources import AmesimStep0, AmesimUd00
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from app.simulation.core.medium import IdealGasMedium
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from app.simulation.registry import COMPONENT_MODEL_REGISTRY
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from app.simulation.solvers.signal import SignalResolver
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from app.simulation.systems.network import SimulationNetwork
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class AmesimSignalComponentTests(unittest.TestCase):
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def setUp(self) -> None:
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self.medium = IdealGasMedium()
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def test_step0_output_switches_at_step_time(self) -> None:
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step = AmesimStep0("step_1", self.medium, initial=0.2, final=0.8, time=0.5)
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self.assertEqual(step.output_at(0.49), 0.2)
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self.assertEqual(step.output_at(0.5), 0.8)
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self.assertEqual(step.signal_output_values(0.5), {"out": 0.8})
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def test_ud00_output_interpolates_piecewise_signal(self) -> None:
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signal = AmesimUd00(
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"piecewise_1",
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self.medium,
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tstart=0.5,
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starts=(0.0, 10.0, 20.0, 0.0, 0.0, 0.0, 0.0, 0.0),
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ends=(10.0, 20.0, 30.0, 0.0, 0.0, 0.0, 0.0, 0.0),
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durations=(1.0, 2.0, 1.0, 0.0, 0.0, 0.0, 0.0, 0.0),
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nstages=3,
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)
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self.assertAlmostEqual(signal.output_at(0.0), 0.0)
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self.assertAlmostEqual(signal.output_at(1.0), 5.0)
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self.assertAlmostEqual(signal.output_at(2.5), 15.0)
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self.assertAlmostEqual(signal.output_at(5.0), 35.0)
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self.assertEqual(signal.signal_output_values(2.5), {"out": 15.0})
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def test_ud00_can_cycle_active_stages(self) -> None:
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signal = AmesimUd00(
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"piecewise_1",
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self.medium,
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starts=(0.0, 10.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0),
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ends=(10.0, 20.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0),
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durations=(1.0, 1.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0),
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nstages=2,
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iscyclic=True,
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)
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self.assertAlmostEqual(signal.output_at(0.25), 2.5)
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self.assertAlmostEqual(signal.output_at(1.25), 12.5)
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self.assertAlmostEqual(signal.output_at(2.25), 2.5)
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def test_ud00_registry_rejects_fractional_stage_controls(self) -> None:
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with self.assertRaisesRegex(ValueError, "nstages must be an integer"):
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COMPONENT_MODEL_REGISTRY["amesim_ud00"].create(
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"piecewise_1",
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self.medium,
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{"nstages": 1.5},
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)
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def test_pnvo001_signal_opening_reads_res_port(self) -> None:
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valve = COMPONENT_MODEL_REGISTRY["amesim_pnvo001"].create(
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"valve_1",
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self.medium,
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{"opening0": 0.25},
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)
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self.assertIsInstance(valve, AmesimPnvo001SignalOpening)
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self.assertEqual(set(valve.ports), {"res", "port_2", "port_3"})
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self.assertAlmostEqual(valve.opening, 0.25)
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valve.res.signal = 1.5
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self.assertAlmostEqual(valve.opening, 1.0)
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valve.res.signal = -0.5
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self.assertAlmostEqual(valve.opening, 0.0)
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def test_signal_resolver_propagates_step_to_valve_input(self) -> None:
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network = SimulationNetwork("signal-smoke")
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step = AmesimStep0("step_1", self.medium, initial=0.0, final=0.75, time=0.1)
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valve = AmesimPnvo001SignalOpening("valve_1", self.medium, opening0=0.0)
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network.add_component(step)
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network.add_component(valve)
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network.connect("step_1", "out", "valve_1", "res", connection_id="signal-1")
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resolver = SignalResolver(network)
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resolver.solve(0.2)
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self.assertAlmostEqual(step.out.signal, 0.75)
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self.assertAlmostEqual(valve.res.signal, 0.75)
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self.assertAlmostEqual(valve.opening, 0.75)
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if __name__ == "__main__":
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unittest.main()
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